1. Field of the Invention
The present invention relates to methodology used in the manufacture of integrated circuit devices, and, more particularly, to a method of detecting the depth of an opening in a dielectric material layer formed on a substrate, such as a semiconductor substrate, so as to adjust critical etch parameters required for accurate control of the depth of the openings.
2. Description of the Related Art
Many fabrication processes in the manufacture of semiconductor integrated circuits (ICs) involve the sequential formation of layers of materials on the wafer surface, which are patterned by photolithographical steps and subsequent etching procedures so as to form structures having feature sizes down to 0.25 micrometers and beyond as is the case in most recent very large scale integration (VLSI) designs. Usually, insulating layers cover most of the surface of the substrate, and windows or openings are formed in the insulating layer through which contacts can be made to underlying electrically conductive regions, or in which devices or features have to be formed. In the manufacturing process of VLSI devices, plasma etch techniques are of immense importance, since these techniques are capable of an anisotropic etching, which is mandatory when feature heights have comparable dimensions to feature line widths and spaces. Generally, these plasma etch techniques provide a considerably higher etch rate in the vertical direction than in the horizontal direction, so that a desired edge profile can be obtained. In order to attain precisely patterned features, such as contact holes and via holes, it is necessary to accurately control the etch rate. However, the etch rate of a given etch process depends on a plurality of parameters such as excitation frequency of the plasma, flow rate of the reactive gases which are provided to form the plasma, pressure of the reactive gases and RF power dissipated in the plasma. Since complicated interdependencies between these parameters exist, it is very difficult to calculate the average etch rate of any etch process so as to determine the time or duration the etch process must be performed to complete the process, i.e., until substantially all of the desired material is removed. Generally, etching is therefore allowed to continue for an over-etch period necessary to compensate any etch rate non-uniformity caused by parameter drifts. Since the erosion of underlying layers, however, should be kept as small as possible, it is important, on the other hand, to minimize the over-etch time. This is particularly true for the critical dielectric contact or via hole etch in modern VLSI devices, wherein openings having a high aspect ratio have to be formed in a thick dielectric layer. In order to maintain a high quality standard in performing critical etch processes, it is necessary to continuously monitor the etch process and steadily readjust process parameters which may slightly drift due to small variations of the etch conditions and the complex mutual relationships of the parameters. For example, increasing amounts of contamination in the process chamber, which depends on the number of wafers that have been etched, leads to a subtle variation of the conditions in the etch process.
Accordingly, in the prior art methodology, the etch depth in forming contact holes and via holes in the dielectric stack is monitored by SEM (scanning electron microscopy) cross-section analysis. To this end, a test wafer is prepared, for example, by depositing a silicon oxide layer having a thickness which corresponds to the required depth of the opening to be formed in the manufacturing process, and an etch process is performed in the etch tool, wherein the parameters of the etch process may be monitored. Subsequently, a few single specimens from the test wafer, preferably from the edge and the center, are cleaved and SEM-inspected. Generally, the preparation of the test wafer and the SEM inspection takes place out of the clean room, i.e., outside of the manufacturing area. In the meantime, the etch equipment may be released for use in production operations so as to avoid any delay of the manufacturing process, with the risk of producing defective integrated circuits, or may be kept on hold until the result of the cross-section analysis is provided. Preparing the test wafer for SEM inspection and carrying out the analysis typically takes at least a few hours. Such a corresponding delay in production significantly contributes to the production cost of the semiconductor device. However, releasing the etch equipment for production prior to receiving the SEM results may yield a large number of processed wafers which do not satisfy the etch specification required for the further processing of these wafers. Thus, in either case, the conventional methodology with respect to etch depth analyses significantly contributes to the overall production costs in the manufacture of VLSI devices.
The present invention is directed to a method that solves or reduces some or all of the aforementioned problems.
According to one aspect of the present invention, there is provided a method of inspecting a depth of an opening in a dielectric material layer formed on a substrate, wherein the method comprises the steps of: depositing a dielectric material layer of a predefined thickness on a surface of the substrate, forming a predefined pattern of openings in the dielectric material layer at at least one predetermined position on the substrate, providing a voltage contrast inspection tool and determining a voltage contrast image of the predefined pattern, comparing the determined voltage contrast image with a reference image corresponding to a voltage contrast image for the predefined pattern with the openings fully opened down to a surface of the substrate, and estimating the amount of dielectric material covering the bottom of the openings based upon the comparison between the measured voltage contrast image and the reference image.
According to a second aspect of the present invention there is provided a method of inspecting a depth of an opening in a dielectric material layer formed on a substrate, wherein the method comprises the steps of: depositing a dielectric material layer of a predefined thickness on a surface of the substrate, forming at least two predefined patterns of openings in the dielectric material layer at respective predetermined positions on the substrate, providing a voltage contrast inspection tool and determining a voltage contrast image of the predefined patterns, comparing the respective voltage contrast images with each other, and estimating the amount of dielectric material covering a bottom of the openings of one of the at least two predefined patterns based upon said comparison of said respective contrast images.
According to the present invention, an efficient and fast method of inspecting patterns on a test wafer with respect to the depth of an opening is provided, since no specimen preparation, such as cleavage of the test wafer, is necessary and the inspection tool is commercially available and may be located within the clean room. In this manner, typically an inspection result or a test wafer may be obtained within several minutes, depending on the number of patterns, compared to several hours or more in the conventional procedure. When a plurality of patterns is distributed over the entire surface of the test wafer, a large amount of information in comparison to the conventional method may be obtained, since a large number of openings may be scanned without the necessity to precisely prepare, i.e., cleave, the test wafer at the plural locations of patterns on the wafer, as is the case in the cross-sectional analysis. Furthermore, the results of the analysis do not depend on conditions of sample preparation as is the case when test wafers have to be cleaved and prepared for cross-section SEM analysis. Accordingly, process parameters of process equipment, such as plasma etch tools, can be monitored and readjusted more often than in the conventional methodology, resulting in an increased yield of reliable products, wherein even the time consumed for obtaining the inspection results is significantly reduced. A further advantage of the present invention resides in the fact that the method is applicable on commercially available SEM tools which are steadily gaining in importance as inspection tools in a process line of a semiconductor facility, so that in many facilities a voltage contrast inspection tool may be available within the clean room. Moreover, in the first aspect of the present invention, i.e., when a pattern on the test wafer is compared to a reference image, it is possible to relate different depths, particularly different etch stop depths of the openings, to different voltage contrast levels, that is, different shades of gray, so as to obtain a qualitative or even quantitative calibration of the inspection tool. Moreover, the present invention provides for the possibility to form complex test patterns and test topographies on the wafer to obtain corresponding voltage contrast images which may correspond to the complex structure on the product wafer to be processed after releasing the process equipment under consideration. Since the wafers inspected according to the method of the present invention no longer need to be cleaved, it is now possible to re-work utilized test wafers for repetitive use. Moreover, one or more product wafers within a lot may be provided with a test die carrying a test pattern so that parameter drift over a plurality of product wafer lots may be continuously monitored without utilizing any test wafer. Further advantages and embodiments are defined in the appended claims.